How capacity (capacitor capacity) is kept is an important consideration for memory devices represented by dynamic random access memories (DRAMs) as their integration degree increases. Capacitor structures broadly fall into two categories, trench capacitors and stacked capacitors, where a silicone substrate is provided with deep grooves in the former and a transistor is located beneath a capacitor in the latter. In each structure, it is necessary to increase capacitor height or decrease dielectric film thickness, in order to increase capacitor capacity. Increasing capacitor height depends on etching capability, and decreasing dielectric film thickness depends on development of high dielectric materials, because thickness of a silicon oxide film is approaching the lower limit. On the other hand, pattern shape itself has an effect on improvement of capacity. Elliptic patterns are now prevailing, replacing truly circular ones, to keep a higher capacity for the same area.
Dry etching is a technique which applies rf power from an external source to an etchant gas introduced into a vacuum chamber to produce a plasma therein, where reactive radicals or ions produced in the plasma are precisely reacted over a wafer to selectively etch a film work while minimizing effects on other materials, e.g., a mask represented by resist and interconnecting layer or base substrate located underneath via hole, contact hole, and storage node in a capacitor.
For forming via holes, contact holes and storage nodes in a capacitor, a mixture of a fluorocarbon gas, noble gas represented by Ar or the like, oxygen gas and so forth is treated at 0.5 to 10 Pa to produce a plasma, and the ion energy hitting a wafer is accelerated to 0.5 to 4.0 kV. The useful fluorocarbon gases include CF4, CHF3, C2F6, C3F6O, C4F8, C5F8, C4F6 and C6F6. The etching technique for these devices has applied bias power to a wafer after a plasma is ignited and sufficiently grown. Applying bias power to a wafer when a plasma is not sufficiently grown or not ignited under some plasma conditions will cause troubles resulting from insufficient or substantially no current flowing into the wafer, with the result that a bias power supply line, electrode on which the wafer is set or wafer itself may be exposed to an abnormally high voltage. These problems, in turn, may cause dielectric breakdown of the bias power supply line, breakdown of a film formed by spraying on the electrode or cracking of the wafer. Therefore, a means for detecting plasma ignition (optical emission intensity monitor) is generally provided for mass production to allow bias power to be applied to a wafer in a certain time after the means detects plasma ignition. At the same time, gas conditions (gas species and flow rate) and cooling gas pressure on the wafer back side are basically kept constant during the etching process. On the other hand, a step etching is proposed (e.g., by Patent Document 1) to produce holes of high aspect ratio at a high mask-selectivity without causing shape abnormality, e.g., boring, in which process steps are changed from each other in accordance with processed aspect ratio or CF-based deposit quantity.
Patent Document 1: JP-A-2002-110647